Silicon single crystal wafers are used mostly as materials forming a semiconductor integrated circuit. Various kinds of stresses are applied to a wafer by a heat treatment or machining until a semiconductor device is formed on a surface layer of a silicon single crystal wafer to provide an integrated circuit. Therefore, a silicon single crystal wafer produced from a silicon single crystal obtained by a Czochralski method (which will be referred to as a CZ method hereinafter) is superior in strength, and hence this wafer tends to be often used.
However, in recent years, with density growth of an integration degree of a semiconductor integrated circuit and attendant miniaturization of a device circuit, a quality requirement for a silicon single crystal as a wafer material is rigidifying. In particular, a grown-in defect that is introduced into a crystal at the time of growing a silicon single crystal has a great effect on characteristics when an integrated circuit is formed on a surface layer of the silicon single crystal wafer, and hence the defect present in the surface layer of a wafer used as a material for a high-function semiconductor device is precisely specified to product the silicon single crystal wafer. Further, in order to fulfill this requirement, in production of a silicon single crystal as a material of the silicon single crystal wafer, various methods of growing a silicon single crystal that can suppress formation of the grown-in defects as much as possible (that can ideally prevent the grown-in defects from being formed at all or can suppress such defects with a very low density even though the defects are formed) have been examined.
In order to grow a low-defect crystal in which the grown-in defect is suppressed, growing the crystal while preferably keeping a cooling rate of the single crystal pulled from a raw material melt constant as much as possible in an area where a defect formation suppressing effect becomes prominent. As disclosed in, e.g., Japanese Patent Laid-open (Kokai) No. H11-79889, when a crystal is grown in a neutral region which is present at a boundary between a V-rich region where a grown-in defect, e.g., a Flow Pattern Defect (FPD), a Laser Scattering Tomography Defect (LSTD), or a Crystal Originated Particle (COP) is generated and an I-rich region where a Large-Secco Etch Pit Defect (L-SEPD) is generated and in which these crystal defects are not present, a silicon single crystal having a high quality can be obtained.
In recent years, a demand for a high-quality silicon single crystal wafer in which crystal defects are suppressed as explained above has been increased. However, it has been revealed that very small crystal defects are present even in a silicon single crystal subjected to crystal growth in a neutral region to suppress such crystal defects. Since such a crystal defect has a very small defect size (a diameter: approximately 15 nm to 20 nm), a particle counter used for regular crystal examination cannot detect such crystal defects. These defects are called Direct Surface Oxide Defects (DSOD), and detected by defect evaluation using Cu (copper) deposition.
The Cu deposition method has characteristics of accurately measuring defect positions in a silicon single crystal and improving a detection limit with respect to defects present in a wafer surface layer, thereby precisely evaluating very small defects. Specifically, an oxide insulating film (which will be also simply referred to as an oxide film hereinafter) having a predetermined thickness is formed on a wafer surface, and the oxide insulating film provided above a position of a defect formed in the wafer surface layer is destructed. Further, Cu is deposited at a position of the destructed oxide film part to specify the defect. When a voltage is applied to the oxide film formed on the wafer surface in a solution in which a Cu ion is present, a current flows through a part where the oxide film is degraded, and the Cu ion is precipitated as Cu. Since it is known that a the Cu precipitation part is a part where a grown-in defect due to a void, e.g., a COP is present, when this part is observed under a collimated light or directly by the naked eye or observed through an optical microscope, a transmission electron microscope (TEM), or a scanning electron microscope (SEM), a distribution or a density of defects can be evaluated.
Although the DSOD can be confirmed by evaluation based on the Cu deposition method, a surface of the wafer must be machined into a mirror surface in evaluation based on the Cu deposition method, and this is usually carried out in the form of sampling inspection after a mirror polishing process that is a final process in wafer processing. However, when the wafer is rejected on this stage, wafer machining is performed even with respect to a rejected lot without exception, and the rejected product takes labor and cost like a conforming product but is finally discarded, which is hence wasteful. Furthermore, the defect is hard to be discriminated from, e.g., a scratch caused by machining, and hence there is a problem in a measurement precision.
As explained above, the DSOD is a small defect having a diameter of approximately 15 to 20 nm, but a void defect (a diameter: approximately 10 to 15 nm) smaller than the DSOD may present in a surface layer of a silicon single crystal wafer. This small void defect may also affect characteristics of an integrated circuit formed on the surface layer of the silicon single crystal wafer in some cases. Therefore, a method that enables accurate and simple evaluation with respect to this void defect smaller than the DSOD has been demanded.